1. Field of the Invention
The present application relates to DRAM and specifically to refresh of a DRAM.
2. Description of the Prior Art
DRAM (dynamic random access memory) has the lowest cost and highest density (cells per unit area) of any type of RAM. However, each DRAM cell (including a transistor and a capacitor) must be periodically refreshed to restore charge to its capacitor as the charge leaks away. During refresh, no other operation to that cell can take place. Usually refresh is done to each row in a DRAM array, one row at a time. During refresh, the DRAM row of cells is turned on and voltage applied to that row of cells to recharge each capacitor in that row. Refreshing adds complexity (cost) to any DRAM system and reduces performance. Refresh usually involves a row address strobe (RAS) for RAS only refresh, and RAS and CAS for the activation of CAS before RAS refresh. To address the DRAM array, the row addresses are applied to the DRAM chip address pins, then strobed in by the RAS signal. The column addresses are then applied to the same set of address pins and strobed in by the CAS signal.
Techniques such as RAS only refresh, CAS-before-RAS refresh, and hidden refresh are commonly used for refreshing DRAM devices in a memory system. These techniques are well documented in the data books of DRAM suppliers, for example, 1991 Memory Products Data Book, NEC Electronics Inc.. In all these techniques, only one row of DRAM cells (in one or more banks) is refreshed at one time, and the refreshed memory bank(s) go(es) through one complete RAS cycle. For RAS only refresh, the row and bank address is supplied externally. For the other types of refresh, the row and bank address are supplied internally by a refresh address counter. In these techniques, sequences of RAS and/or CAS signals are used to instruct the memory device to enter a refresh cycle.
These prior art approaches either reduce system performance or require excessive intervention from the memory controller to perform refresh.